Application Engineer – Simulation Consultant

• B.Sc in Electrical or Computer Engineering. • 3+ years of relevant experience in digital design verification, RTL simulation, or EDA application engineering. • Strong knowledge of Verilog/SystemVerilog, VHDL, micro-architecture, and digital logic design. • Hands-on experience with simulation tools and debugging methodologies. • Proficiency in Unix/Linux environments and scripting using Bash, CSH, TCL, Perl, or Python. • Excellent communication skills in English.